The present invention relations to power-on-reset circuits, and to integrated circuits which are battery-powered.
A problem in many integrated circuits is detection of the initial power-on state. There are many functions which may need to be performed at initial power-on, such as self-testing, clearing garbage data from memory.sup.1 and restoring all elements to a known state, and loading saved data. FNT .sup.1 When power is removed and reapplied, many circuit elements (such as the latch in a conventional SRAM cell) will assume an unpredictable logic state.
This is particularly useful for battery-backed or battery-operated integrated circuits, which may be used to perform power-management or nonvolatizing functions for an electronic system. If such a component has lost its battery power, it may lose its valid data, and may begin to issue erroneous commands to the system.
Thus, a great many types of integrated circuits include a "power-on-reset" circuit. This circuit detects when power is applied after a power-down condition, and issues a reset pulse which is used to initiate performance of the above functions.
There are two main objectives in selecting a power-on-reset circuit: First, the circuit must NOT generate the reset pulse when not needed. Second, the circuit must generate the reset pulse quickly when it is needed.
It is surprisingly difficult to meet both of these objectives. One problem is that integrated circuits are commonly subjected to low-energy electrostatic discharge (ESD) pulses. An ESD pulse on a power supply lead can easily cause a transient increase of tens of Volts on the power supply line, without damaging the chip or even disturbing its data. If such ESD events are allowed to cause a power-on-reset event, the power-on-reset will cause the loss of more data than the ESD pulse itself. This is undesirable.
The opposite problem arises when measures are taken to reduce oversensitivity to voltage surges on the power supply. If the power-on-reset circuit fails to generate a reset pulse when needed, that too can be disastrous.
Moreover, it is desirable to generate the reset pulse quickly, before circuit elements on the chip have time to settle into an undesirable state (which is possible with some circuit architectures).
Some published discussions of these problems may be found in U.S. Pat. Nos. 3,895,239, 4,013,902, 4,591,745, 4,633,107, 4,670,676, 4,818,904, and 4,874,965, all of which are hereby incorporated by reference.
The present invention provides a new power-on-reset circuit, and a new integrated circuit architecture incorporating such a reset circuit. The present invention, like conventional power-on reset circuits, uses an integration capacitor to power, with a weak pull-down to ground, followed by an inverter chain, as an initial pulse-generating circuit. This circuit element produces a pulse, as desired, when power is first applied. Such a pulse can be propagated through to provide the desired power-on reset pulse. However, this circuit element will also produce a pulse if a transient voltage increase is seen on the power supply line. This means that an ESD hit, even if it is not severe enough to damage the devices, may still cause the loss of all data on chip, by activating the power-on reset circuit incorrectly. This is undesirable.
The presently preferred embodiment includes a totally symmetric cross-coupled pair of gates. Since this circuit is symmetric, its state at the time power is first supplied will be unknown. However, due to the cross-coupling of this circuit, it will settle into one of two possible states. The two outputs of this flip-flop are carried forward separately.
After an intervening stage (described below), each of these cross-coupled gates is followed by a blocking gate, where the output of the cross-coupled gate is combined with the output of the initial pulse-generating circuit. Initially, one of the cross-coupled gates will have a state which permits propagation of the pulse from the initial pulse-generating circuit.
The blocking gates are both fed into a combining gate, so that, if a reset pulse has propagated through either of the blocking gates, it will propagate on through the combining gate.
The additional intervening stage mentioned above is a strongly asymmetric gate (an inverter, in the presently preferred embodiment). Until the cross-coupled gates propagate their state, these asymmetric inverter provide an output which is dominated by their strong side (the pull-up side, in the presently preferred embodiment). Thus, in the presently preferred embodiment, nodes A* and B* will initially follow the power supply voltage up, until one of the nodes A or B goes low enough to switch the following inverter.
A signal from a later state of propagation is fed back to disable the fully symmetric flip-flop. By the time the flip-flop is disabled, the initial power-on reset pulse will have already propagated through.